1. Field of the Invention
The present invention relates to a solid-state image pickup device in which a plurality of pixels including photodiodes and transfer gate electrodes are disposed in a pixel region of a semiconductor substrate and more particularly, to a solid-state image pickup device in which 2 adjacent pixels share a part, including a floating diffusion, of circuits.
2. Description of the Background Art
In recent years, there has been an increasing demand for downsizing and high resolution of an image pickup device such as a CCD-type and a MOS-type image sensor (CMOS process compatible sensor). Since reducing an area per unit pixel is effective in meeting this demand, a variety of circuit designs have been conventionally devised.
FIGS. 10A and 10B are circuit diagrams illustrating examples of pixel parts of the CMOS process compatible sensor (hereinafter, referred to as a CMOS sensor) which has been conventionally proposed (for example, refer to the specification of U.S. Pat. No. 6,033,478). FIG. 10A shows an example of a 4-transistor-type CMOS sensor in which 4 transistors are required for 1 pixel and FIG. 10B shows an example of a 3-transistor-type CMOS sensor in which 3 transistor are required for 1 pixel. In specification of the present invention, in order to facilitate understanding, common reference numerals are used for common functional components in FIGS. 10A and 10B.
In FIG. 10A, a pixel pair 1 comprises 2 pixels 2a and 2b in adjacent rows. The pixels 2a and 2b comprise photodiodes 3a and 3b (hereinafter, referred to as PD 3a and PD 3b) and transfer gate electrodes 4a and 4b, respectively. On the other hand, the 2 pixels 2a and 2b share a floating diffusion 5 (hereinafter, referred to as FD 5), a reset transistor 6, an amplifier transistor 12, and a selection transistor 13. A transfer transistor comprises PDs 3a and 3b, a transfer gate electrode 4, and FD 5.
A pixel pair 1 shown in FIG. 10B has a configuration in which the selection transistor 13 is removed from a configuration of the pixel pair 1 shown in FIG. 10A, thereby attaining a reduction in an area. In the meantime, details of a general CMOS sensor in which FD 5 is not shared are disclosed, for example, in Japanese Laid-Open Patent Publication No. 9-46596.
Here, processes performed by circuits shown in FIGS. 10A and 10B will be briefly described. Signal charges accumulated in PDs 3a and 3b in an exposure period are transferred to FD 5 when a predetermined voltage is applied to the transfer gate electrodes 4a and 4b. Then, a potential of a gate of the amplifier transistor 12 is of a magnitude corresponding to a quantity of the signal charges transferred to FD 5, and a voltage signal generated by transforming a reference voltage VDD appears on a vertical signal line 15. In order to prevent blooming, the reset transistor 6 is controlled to be ON when exposure is performed on PDs 3a and 3b and the reference voltage VDD is applied to FD 5. Thus, since the charges in FD 5 are discharged externally, FD 5 is controlled to be in an initial state.
In the meantime, although a layout which realizes the above-mentioned circuits is not disclosed in specification or the like of the above-mentioned U.S. Pat. No. 6,033,478, a layout in general is as shown in FIG. 11. Specifically, the transfer gate electrodes 4a and 4b are disposed diagonally to light receiving regions 20a and 20b of the 2 PDs 3a and 3b adjacent in a column direction (y-axis direction). And FD 5, source and drain regions of the reset transistor 6, and source and drain regions of the amplifier transistor 12 are disposed in order in a row direction (x-axis direction). FIG. 12 is a diagram illustrating a view in which the pixel pair 1 in a layout shown in FIG. 11 is disposed in a pixel region in a matrix manner.
Inventors of the present invention found that when masks for forming the light receiving regions 20a and 20b of PDs 3a and 3b are disposed in a misaligned manner, a problem would arise. More specifically, although the masks should be disposed so that openings 22a and 22b of resist patterns are formed as shown in FIG. 13, when the openings 22a and 22b are disposed as shown in FIG. 14 due to misalignment, characteristics or the like of transfer transistors of respective pixels are changed. When the characteristics or the like of the transfer transistors are changed, sensitivity characteristics of the pixels 2a and 2b fluctuate and an image having a fine quality cannot be obtained, leading to a fatal flaw of the solid-state image pickup device.